Kingswood Consulting - FPGA

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FPGA Design Flow

To implement a design in FPGA, specific EDA tools are required that understand the FPGA structure and how to map RTL to the FPGA lookup tables and interconnects. As a rule, ASIC tools can not be used for FPGA synthesis.

FPGA vendors supply (often at minimal cost) design tools that target their products. In recent years the VHDL and Verilog front ends on these tools have been improved greatly, and it is no longer necessary to use a separate compiler. The vendor EDA tools also have the best support for their newest FPGAs.

In some cases, using a vendor independent front-end such as Synplicity or Mentor Precision is desirable. Often, the front-end compiler produces a netlist that is placed and routed in the back-end of the vendor-supplied tool, but some tools support multi-vendor physical synthesis.

FPGA verification

Where an FPGA implementation is used for verification of a design that is intended for implementation in an ASIC it us usually necessary to make changes to the clocking, reset and I/O structures to fit the design in the limits of the FPGA. Encapsulating these differences is necessary to ensure the ASIC's functionality is not accidentally altered.

RTL simulations using FPGA specific library components is used to verify that the design works correctly with the I/Os, memories and other macros in the FPGA.

Timing constraints are supplied either as an SDC file or using the EDA tool's graphical user interface. After synthesis and place and route, timing analysis establishes the constraints were met. Sometimes timing violations are ignored, especially if they are on non-critical I/Os or violate the constraints only minimally.

Gate level simulations on FPGA designs are very occasionally done to check behaviours seen in the hardware. In most cases, debugging can proceed on the target hardware, using synthesized debugging signals or unused logic gates and unrouted pins connected to external test equipment. Most FPGA vendors offer embedded logic analyser cores that allow a limited amount of high speed data capture into internal memories.